Abstract

In modern integrated circuit (IC) designs with feature size finer than 90nm, the stress among different material layers is playing an important role in determining device performance. The stress can be classified into two categories, stress deliberately introduced during semiconductor process, and stress unintentionally formed through the synergy of different processing steps. Among different types of inadvertent stresses, Shallow trench isolation (STI) stress which is exerted from the isolation materials is the primary one that has a major impact on circuit characteristics. A detailed analysis of STI stress on an IC chip, however, is a complicated process because the stress is determined by the distribution of layout patterns, which could add up to trillions in today's typical IC designs. The traditional technology computer aided design (TCAD) tools for such an analysis are already too slow on large circuits. In this work, a GPU-based finite element simulator for full chip stress analysis is developed. Experimental results showed that the GPU-based simulator could outperform its CPU equivalent by a factor of 20X. Such a speedup would allow detailed stress-aware performance optimization for large ICs.

Paper available at IEEE.

Abstract

Loopy belief propagation (BP) is an effective solution for assigning labels to the nodes of a graphical model such as the Markov random field (MRF), but it requires high memory, bandwidth, and computational costs. Furthermore, the iterative, pixel-wise, and sequential operations of BP make it difficult to parallelize the computation. In this paper, we propose two tech-niques to address these issues. The first technique is a new mes-sage passing scheme named tile-based belief propagation that reduces the memory and bandwidth to a fraction of the ordinary BP algorithms without performance degradation by splitting the MRF into many tiles and only storing the messages across the neighboring tiles. The tile-wise processing also enables data reuse and pipeline, resulting in efficient hardware implementation. The second technique is an O(L) fast message construction algorithm that exploits the properties of robust functions for parallelization. We apply these two techniques to a VLSI circuit for stereo matching that generates high-resolution disparity maps in near real-time. We also implement the proposed schemes on GPU which is four-time faster than standard BP on GPU.

Paper available at IEEE.

Abstract

In this paper, we discuss our approach on the GPU implementation of the Discontinuous Galerkin Time-Domain (DGTD) method to solve the time dependent Maxwell's equations. We exploit the inherent DGTD parallelism and combine the GPU computing capabilities with the benefits of a local time-stepping strategy. The combination results in significant increase in efficiency and reduction of the computational time, especially for multi-scale applications.

Paper available at IEEE.

Abstract

In this paper, a new three- dimensional particle beam simulation using a high performance hardware is introduced. The graphics processing unit (GPU) hardware is highly parallel and has low-cost computational capabilities. The code uses NVIDIA CUDA programming model and a particle trajectory integration steps on the graphics hardware, in a standard 4th-order Runge-Kutta scheme. The model uses mesh less representations for electromagnetic fields, based on either analytic formulas or field expansion techniques, to achieve a high degree of parallelism in the calculations. The author describe potential applications of the code for 3D simulation of vacuum electronic devices, and present details of both the algorithms used and simulation performance results.

Paper available at IEEE.

Abstract

For voltage source inverter (VSI) based power supply with small filter inductor, the current ripple of the power switch is large especially under light load conditions. The dead-time effect in this situation is analyzed in this paper. The results show that the dead-time effect is eliminated at most zero-crossing instants of the current. Conventional dead-time compensation methods either average voltage based or pulse based cannot be adopted in this case because the current polarity changes many times within one fundamental period. A closed-loop method for dead-time compensation is proposed for this condition. The proposed method does not need the detection of the current polarity or any extra hardware and is very easy to implement. Experimental results on a DSP controlled three-phase 400 Hz GPU show that the low-order harmonics introduced by the dead-time in the output voltage are almost eliminated completely.

Paper available at IEEE.