Deep reactive ion etching (DRIE) technique is a new and powerful tool in Micro-Electro-Mechanical Systems (MEMS) fabrication. A 3D DRIE simulation can help researcher understand the time-evolution of Bosch process used in DRIE. Due to the high complexity of the algorithm used in the simulation, it is necessary to develop an algorithm that can accelerate the simulation. This paper presents a parallel implementation of the 3D DRIE simulation based on GPU, built on Nvidia‘s Compute Unified Device Architecture (CUDA) platform. This paper also presents a fast morphological operation, which reduces the complexity of mathematical morphology operation part of the algorithm from ${O(N^3)}$ to ${O(N^2)}$. The experiment results show the parallel program on Nvidia GTX260+ GPU obtains about 70x to 75x speedup over the 4-threads parallel version on Intel Q6600 CPU.

Paper available at ACM.

Recently general purpose computing on graphic processing units (GPUs) is rising as an exciting new trend in high-performance computing. Thus it is appealing to study the potential of GPU for Electronic Design Automation (EDA) applications. However, EDA generally involves irregular data structures such as sparse matrix and graph operations, which pose significant challenges for efficient GPU implementations. In this paper, we propose highperformance GPU implementations for two important irregular EDA computing patterns, Sparse-Matrix Vector Product (SMVP) and graph traversal. On a wide range of EDA problem instances, our SMVP implementations outperform all published work and achieve a speedup of one order of magnitude over the CPU baseline. Upon such a basis, both timing analysis and linear system solution can be considerably accelerated. We also introduce a SMVP based formulation for Breadth-First Search and observe considerable speedup on GPU implementations. Our results suggest that the power of GPU computing can be successfully unleashed through designing GPU-friendly algorithms and/or re-organizing computing structures of current algorithms.

Paper available at ACM.

Abstract:
Logic simulation is a critical component of the design tool flow in modern hardware development efforts. It is used widely -- from high-level descriptions down to gate-level ones -- to validate several aspects of the design, particularly functional correctness. Despite development houses investing vast resources in the simulation task, particularly at the gate-level, it is still far from achieving the performance demands required to validate complex modern designs.

In this work, we propose the first event-driven logic simulator accelerated by a parallel, general purpose graphics processor (GP-GPU). Our simulator leverages a gate-level event-driven design to exploit the benefits of the low switching activity that is typical of large hardware designs. We developed novel algorithms for circuit netlist partitioning and optimized for a highly-parallel GP-GPU host. Moreover, our flow is structured to extract the best simulation performance from the target hardware platform. We found that our experimental prototype could handle large, industrial scale designs comprised of millions of gates and deliver a 13x speedup on average over current commercial event-driven simulators.

Paper available at ACM.

Abstract:
Engineering surfaces are characterized by the form, waviness and roughness features that are comprised of a range of spatial wavelengths. Filtering techniques are commonly adopted to separate these different wavelength components into well-defined bandwidths for further processing. The Gaussian filtered surface in which a 2D Gaussian filter is employed for surface assessments has been recommended by the ISO 11562-1996 and ASME B46-1995 standards to establish a reference surface. For Gaussian filtering, computational efficiency is a key problem when it is issued on a large set of surface metrology data. In the past this problem was tackled through reducing computation amount by the design and adoption of some fast algorithms. In this paper, a General Purpose Computing on GPU (GPGPU) framework is discussed to accelerate 2D Gaussian filtering for surface characterization. This framework takes advantage of the GPU’s parallel computing ability and has achieved better data efficiency without reducing the computational amount while maintaining the filtering quality. Filtering results and their accuracy from this model have been compared with the results obtained from the MATLAB simulation kits and the satisfied outcomes were observed.

Paper available at ACM.

Abstract:
Integrated circuit (IC) design automation has traditionally followed a hierarchical approach. Modern IC design flow is divided into sequentially-addressed design and optimization layers; each successively finer in design detail and data granularity while increasing in computational complexity. Eventual agreement across the design layers signals design closure. Obtaining design closure is a continual problem, as lack of awareness and interaction between layers often results in multiple design flow iterations. In this work, we propose parallel cross-layer optimization, in which the boundaries between design layers are broken, allowing for a more informed and efficient exploration of the design space. We leverage the heterogeneous parallel computational power in current and upcoming multi-core/many-core computation platforms to suite the heterogeneous characteristics of multiple design layers. Specifically, we unify the highlevel and physical synthesis design layers for parallel cross-layer IC design optimization. In addition, we introduce a massively-parallel GPU floorplanner with local and global convergence test as the proposed physical synthesis design layer. Our results show average performance gains of 11X speed-up over state-of-the-art.

Paper available at ACM.