Abstract:

The paper presents efficient technique for full wave 3D EM modeling of electrically large arrays. Basically it consists in two steps: 1) the network parameters (Y,Z,S) of the array are calculated together with its radiation patterns when each of the elements is active, while all other elements are short-circuited; 2) radiation patterns are obtained by arbitrary combinations of feeding voltages by post-processing data from the first step. 3D EM modeling is facilitated decomposing the problem having geometrical symmetry and asymmetrical excitation into four fully symmetrical problems of quarter size. Matrix solution is accelerated using graphical processor unit (GPU). Thus, array problems of 400 and 900 microstrip patch antennas become doable in 6 hours and 1 day, respectively.

Paper available at IEEE.

Abstract:

We present results for frequency-domain MoM simulations of electrically large structures using out-of-core solver accelerated with multiple GPUs on a single personal computer. The structures analyzed in order to demonstrate the efficiency of proposed out-of-core solver are Cassegrain reflector antenna with up to 240 λ reflector diameter and Luneburg lens, up to 16 λ diameter, excited with a half-wavelength dipole. The acceleration of out-of-core solver is up to 10 times with one GPU compared to a standard CPU, or up to 20 times when using 3 GPUs.

Paper available at IEEE

Abstract:

With the rising challenges in heat removal in integrated circuits (ICs), the development of thermal-aware computing architectures and run-time management systems has become indispensable to the continuation of IC design scaling. These thermal-aware design technologies of the future strongly depend on the availability of efficient and accurate means for thermal modeling and analysis. These thermal models must have not only the sufficient accuracy to capture the complex mechanisms that regulate thermal diffusion in ICs, but also a level of abstraction that allows for their fast execution for design space exploration. In this paper, we propose an innovative thermal modeling approach for full-chips that can handle the scalability problem of transient heat flow simulation in large 2-D/3-D multiprocessor ICs. This is achieved by parallelizing the computation-intensive task of transient temperature tracking using neural networks and exploiting the computational power of massively parallel graphics processing units. Our results show up to 35× run-time speedup compared to state-of-the-art IC thermal simulation tools while keeping the error lower than 1°C. Speedups scale with the size of the 3-D multiprocessor ICs and our proposed method serves as a valuable design space exploration tool.

Paper available at IEEE.

Abstract:

In this paper, we present RAG, an efficient Reliability Analysis tool based on Graphics processing units (GPU). RAG is a fault injection based parallel stochastic simulator implemented on a state-of-the-art GPU. A two-stage simulation framework is proposed to exploit the high computation efficiency of GPUs. Experimental results demonstrate the accuracy and performance of RAG. An average speedup of 412× and 198× is achieved compared to two state-of-the-art CPU-based approaches for reliability analysis.

Paper available at IEEE.

Abstract:

With the fast increasing complexity of integrated circuits, verification has become the bottleneck of today‘s IC design flow. In fact, over 70% of the IC design turn-around time can be spent on the verification process in a typical IC design project. Among various verification tasks, Register Transfer Level (RTL) simulation is the most widely used method to validate the correctness of digital IC designs. When simulating a large IC design with complicated internal behaviors (e.g., CPU cores running embedded software), RTL simulation can be extremely time consuming. Since RTL-to-layout is still the most prevalent IC design methodology, it is essential to speedup the RTL simulation process. Recently, General Purpose computing on Graphics Processing Units (GPGPU) is becoming a promising paradigm to accelerate computing-intensive workloads. A few recent works have demonstrated the effectiveness of using GPU to expedite gate and system level simulation tasks. In this work, we proposed an efficient GPU-accelerated RTL simulation framework. We introduce a methodology to translate Verilog RTL description into equivalent GPU source code so as to simulate circuit behavior on GPUs. In addition, a CMB based parallel simulation protocol is also adopted to provide a sufficient level of parallelism. Because RTL simulation lacks data-level parallelism, we also present a novel solution to use GPU as an efficient task-level parallel processor. Experimental results prove that our GPU based simulator outperforms a commercial sequential RTL simulator by over 20 fold.

Paper available at ACM.